1. Field of the Invention
The present invention relates generally to the field of active semiconductor devices. More specifically, the present invention relates to active devices referred to as normally off Junction Field Effect Transistors (JFET). More particularly, the present invention relates to a novel device structure for an asymmetrical, normally off JFET useful in low voltage and high current density applications.
2. Related Art
The increasing trend toward lower supply voltages for active semiconductor devices and Integrated Circuits (IC""s) has accelerated the search for more efficient low voltage power sources. Conventional power supplies utilizing silicon diode rectifiers are unacceptable in low voltage applications due to the excessive voltage drop across the forward biased diode terminals. Power loss in the diodes becomes excessive when they are used as rectifiers in a DC power supply designed for a terminal voltage as low as 3.0 volts.
Semiconductor diodes are combined with active devices to form circuits capable of producing low value DC supply voltages, but such circuits are generally not capable of handling the large currents frequently required. They usually exhibit a fairly large internal resistance and as such are very inefficient power sources. Furthermore, the number and complexity of steps required in the processing of this type of circuit as an IC also increases with the number of devices included.
Active semiconductor devices are used as switches in circuit arrangements producing DC power supply voltages, as for example in switched mode power supplies. Junction Field Effect Transistors (JFET) are frequently used as switches because they are easily switched between an ON or conducting state and an OFF or non-conducting state. Most importantly, the current carriers in a JFET are all majority carriers which results in short switching times. However, when operated at lower voltages, JFETs exhibit an internal resistance in the ON state that make them unsatisfactory and inefficient in applications requiring large currents.
In U.S. Pat. No. 4,523,111 entitled xe2x80x9cNormally-Off Gate-Controlled Electric Circuit with Low On-Resistancexe2x80x9d, Baliga disclosed a JFET serially connected to an Insulated Gate Field Effect Transistor (IGFET). The ON resistance of this circuit is the sum of the JFET resistance and the IGFET resistance. As a result, the ON resistance is too large and therefore unsatisfactory for low voltage operations requiring large currents.
In a similar invention disclosed in U.S. Pat. No. 4,645,957 entitled xe2x80x9cNormally Off Semiconductor Device with Low On-Resistance and Circuit Analoguexe2x80x9d by Baliga, a JFET is serially connected to a Bipolar Junction Transistor (BJT). The ON resistance is the sum of the JFET and the BJT which is again too large for low voltage applications requiring large currents.
In an invention disclosed in U.S. patent application Ser. No. 60/167,959, xe2x80x9cSTARTER DEVICE FOR NORMALLY OFF JFETSxe2x80x9d, Ho-Yuan Yu, filed Nov. 29, 1999, a normally OFF JFET is combined in parallel with one or more active devices defined as starter devices. In a first case, a BJT acting as the starter device is connected in parallel with the normally OFF JFET. In a second case, a Metal Oxide Silicon Field Effect Transistor (MOSFET) acting as the starter device is connected in parallel with the normally OFF JFET. In a third case, three normally OFF JFETs are connected serially as a starter device, and are then connected in parallel with the normally OFF JFET. Each of the resulting structures provide high current carrying capacity at low voltage levels, but still exhibit a larger than desired internal resistance in the ON or conducting state. Furthermore, the required starter devices all necessitate an increase in the number of steps and in the complexity of the IC processing recipe.
Accordingly, what is needed is a semiconductor device that can efficiently supply the DC currents required in both discrete and integrated circuits being operated at low DC supply voltages. What is further needed is a semiconductor device that has a very low internal resistance such that the power dissipated in the device itself is only a fraction of that delivered to a connected load. What is needed yet is a semiconductor device that exhibits short switching times between an ON or conducting state and an OFF or non-conducting state. What is also needed is a semiconductor device composed of a minimal number of elements such that the manufacturing process for the device is simplified. The present invention provides these advantages and others not specifically mentioned above but described in the sections to follow.
A semiconductor device that can efficiently supply the DC currents required in both discrete and integrated circuits being operated at low DC supply voltages is disclosed. The device disclosed in the present invention is an asymmetrical, enhancement mode, Junction Field Effect Transistor (JFET). The device consists of an epitaxial layer on the surface of a substrate, both of which are doped with the same polarity. The epitaxial layer has a graded doping profile with doping density increasing with distance from the substrate. A grill-like structure is constructed within the upper and lower bounds of, and extending throughout the length and width of the epitaxial layer, and is doped with a polarity opposite to that of the epitaxial layer. A first electrical connection made to the exposed side of the substrate is defined as the drain electrode. A second electrical connection made to the exposed surface of the epitaxial layer is defined as the source electrode. Finally, a third electrical connection made to the grill-like structure is defined as the gate electrode. The asymmetrical, enhancement mode JFET is thus produced as a three terminal device, with a minimal number of elements and a simplified manufacturing process.
In integrated circuit applications, an asymmetrical, enhancement mode JFET can be manufactured in a well located within and doped with a polarity opposite to the epitaxial layer. A p-channel JFET can be produced in a p-well located within an n-type epitaxial layer. Likewise, an n-channel JFET can be produced in an n-well located within a p-type epitaxial layer. Thus it is possible to produce an integrated circuit having both n-channel and p-channel JFETS.
With no applied difference in electric potential between the gate and either the source or the drain, the built-in p-n junction depletion regions surrounding the grill-like gate structure will form a continuous depletion region that isolates the source region from the drain region. The result is a normally OFF or enhancement mode JFET, since no electric current can exist between source and drain. Application of an electric potential difference that will forward bias the p-n junction between gate and either source or drain will reduce the extent of the p-n junction depletion regions to produce conducting channels between source and drain, thus switching the JFET into the ON or conducting state.
The JFET disclosed in the present invention is referred to as asymmetrical since the graded doping profile of the epitaxial layer causes the p-n junction depletion region on the source side of the gate structure to be narrower than on the drain side. As a result, the gate structure can be located physically closer to the source lead which shortens the conduction channels. The result is a reduction in the electrical resistance of the channels between source and drain when the JFET is operating in the ON or current conducting state. By these means, the time required for switching the JFET between an ON or conducting state and an OFF or non-conducting state is also shortened. Furthermore, because of the asymmetrical structure and an initial parasitic bipolar transistor action, this asymmetrical JFET can be switched between states without the requirement of any starter device connected between the source and the drain. Elimination of the starter device required with previous devices greatly simplifies both the structure and the manufacturing process of the JFET disclosed in the present invention.